About Interconnect
Overview
The Interconnect Focus Center (IFC) conducts research to discover and invent new electrical, optical and thermal interconnect solutions that will meet or exceed ITRS projections and enable hyper-integration of heterogeneous components for future terascale systems. The IFC was founded in 1998 to research all aspects of the wiring that connect the millions of transistors on a microchip, from process to system-level architecture. Today and in the future, the microelectronics and nanotechnology industries will lead the evolution of technology in industries from automotive to medical, and from computing to aviation. The IFC strives to stay atop all advances in these fields and play a major role in driving this technology into the future. To that end, the center's research themes have evolved to accommodate this goal. |
 Dr. Paul Kohl, Center Director |
Research Focus
Exacerbating factors pertaining to the copper-based interconnect schemes for use in future sub-50 nanometer generations of silicon technology drive the need to invent new interconnect solutions. The research focus in the IFC is to discover and invent electrical, optical and thermal interconnect solutions that enable hyper-integration of heterogeneous components. The approach is to capitalize on the enormous amount of research being conducted in nanoscience and technology to develop novel high conductance electrical interconnects to replace copper. Our research also identifies and explores the opportunities and barriers for optical interconnects that will scale to meet the needs of future gigascale silicon electronic systems with emphasis on input/output and global on-chip interconnects.
Interconnect-driven circuit and system design, and modeling are investigated to understand the fundamental trade-offs between electrical and optical interconnections for short-haul communication. In view of the foreseen technology roadblocks of power delivery and thermal management, novel approaches in these areas will be explored.
Research in Interconnect addresses the following four themes:
- Electrical Interconnects
- Optical Interconnects
- Thermal Management and Power Delivery
- Circuit and System Design and Modeling
Theme I, Electrical Interconnects explores new frontier concepts and innovative approaches for the development of both hybrid and monolithic ultra-high performance nanoscale interconnect architectures that mitigate signal delay and heat dissipation problems encountered in traditional electrical interconnects. To that end, Theme I implements three complementary thrusts that explore novel interconnect solutions, namely, ballistic electron transport in molecular wires and carbon nanotubes and spin-packet signal propagation in spintronic systems.
Theme II, Optical Interconnects has the overarching vision to create high-speed, low-power optical interconnects – on-chip, off-chip and in chip-to-network connections – in a platform that is directly compatible with, and an extension of, mainstream future CMOS fabrication. There are many areas of science and technology worthy of research and development in optical interconnects.
The overarching objective of Theme III is to understand and quantify the thermal and power management issues for future ICs, create new solutions to meeting future thermal and power management targets, create the technology for multi-functional chip connections, and make use of advances in materials (especially nanotechnology) in different levels of the interconnect hierarchy. The goal for Theme III is to create the technological solutions for cooling and power delivery for future integrated circuits. In addition, Theme III is also introducing new materials and structures for chip connections.
The mission of Theme IV is to create circuit and system design and modeling approaches to enable future highly interconnected and integrated systems. The first objective is the development of circuit design and modeling approaches to take advantage of the novel and emerging interconnect components (such as nanowires and carbon nanotubes) being investigated in the Center. These unique new components complement rather than fully replace deeply scaled IC technologies, and thus a second high-level objective of Theme IV is to explore non‑conventional circuit and architectural approaches based on both scaled and novel interconnect technologies, in support of aggressive signal, clock, power, and I/O distribution requirements. We are developing new models for novel interconnect components; analysis methods for large systems of these components; circuits and architectures (enabled in part by these new modeling and analysis methods) that leverage novel components; and non-conventional circuits/architectures that overcome power bottlenecks in critical signal, clock, and I/O.
The center is also pursuing two Design Drivers:
Driver I is a futuristic high performance, hypothetical, network routing/computing chip which stresses interconnects to the extreme. Driver I strives to achieve two broad goals: First, it helps in identifying and focusing attention on those critical projects whose solutions do not exist today. Second, it provides a powerful system-aware framework to assess the potential of new interconnect solutions. We are pursuing a Driver I chip which demands requirements significantly higher than what is available in current systems. Drive I integrates all four IFC Themes and couples closely with the GSRC and C2S2 MARCO centers.
Driver II consists of integrated nano-scale non-metallic conductors and devices built on a CMOS platform. Sensing serves as the system function that drives development of interconnect synthesis and assembly technologies, as well as physical, equivalent-circuit, and metrological models and development of new design methodologies that accommodate interconnect property variations. Properties of assembled systems of carbon nanotube (CNT), quantum molecular conductor (QMC), and spin-based interconnects (SPI) elements are bebing measured, and the relative merits of different materials synthesis and assembly techniques are being assessed. Integration of non-metallic interconnects with semiconductor nanowire and CNT devices drive development of design methodologies, as well as development of associated assembly and integration technologies. Driver II integrates all four IFC Themes and is closely coupled with the FCRP’s FENA, MSD, and C2S2 centers.
More information about Interconnect research themes
Center Management
Overall leadership and management of the Interconnect Focus Center (IFC) for Hyper-Integration is the responsibility of the Director, Professor Paul A. Kohl of Georgia Tech, who serves as Chairman of the IFC Leadership Council. The Leadership Council typically confers by telephone on a biweekly basis. An Associate Director and an Administrative and Financial Manager also participate in Leadership Council meetings. The Administrative and Financial Manager also serves as Chairperson of the IFC Administrative Committee composed of members from each of the five major sites of the IFC. The IFC Administrative Committee facilitates budget actions, annual program reviews and quarterly workshops of the center. |
 The Interconnect Focus Center operates under the direction of Dr. Paul Kohl of Georgia Tech. |
